LABORATORY III ON ELECTRONICS
Last update : November 1999    Spanish Version    
OBJECTIVES:

At the end of the course, the student will:

CONTENTS

CYCLE I: HARDWARE SYNTHESIS (20H)

METHODOLOGIES FOR HARDWARE DEVELOPMENT AND HARDWARE DESCRIPTION  LANGUAGES (HDLs) (2H)

The problem of the complexity of real systems. Structuring the solution. Bottom-Up and  Top-Down approaches. Discrete components vs. ASICs. Development cycle using CASE tools.

VHDL (4H)

Description of combinational and secuential circuits. Structures and subsystems. Libraries of components. Description of complete  systems .

HARDWARE SYNTHESIS CASE TOOL (4H)

- Input languages : VHDL, Finite State Machines , Time diagrams , others.
- Operation of the CASE tool. Specification and simultation-testing of circuits using VHDL.
- Most important commercial families.. PLDs Synthesis.

CYCLE II: EMBEDDED SYSTEMS (40H)

PROTOTYPING (4H)

Fundamentals. Rapid prototyping (discardable prototypes) vs. evolutionary prototyping. Spiral approach to the development of software systems(Boehm), variants: Development by phases, waterfall+spiral development, evolutionary development and delivery.

STRATEGIES FOR DEVELOPING EMBEDDED SYSTEMS (6H)

- Lyfe cycle : User's manual, evolutionary development and delivery, development by phases, definition of each delivery (risk-based).
- Crossed-development. using discardable prototypes and portable prototypes. Code portability, implementation considerations.
 

METHODOLOGY

This course is practical. The distribution of time is approx. 20% in lectures and 80% in lab practices.
At the end of the first cycle the teams must deliver a small hardware synthesis project, in the 5th. week.
The final project is an embedded systems developed incrementally and controlled by the instructor in a weekly basis, according to the project's plan.
The teams will be made up of 4 people (exceptionally 3 if  the instructor allows it) and each member will have specific functions.
The projects change each semester and CANNOT be repeated.